In semiconductor fabrication, thermal stress is a major consideration in designing the interface between a semiconductor integrated circuit (IC) chip and the package substrate to which it is mounted. The package substrate has a high coefficient of thermal expansion (CTE) compared to the silicon of the IC chip. For example, the package substrate may have a CTE of about 15 ppm/deg. C., while the IC chip has a CTE of about 3 ppm/deg. C. In a flip-chip packaging process, after the IC has been mounted to the package substrate, a large change in temperature would result in differential expansion or contraction between the substrate and the IC. This differential expansion will induce warpage, causing warpage-induced damage. In the presence of warpage, it is likely that the solder bumps (connecting the contact pads of the IC to the contacts of the package substrate) will crack.
Various techniques have been developed to prevent damage due to CTE mismatch between the IC substrate material and the package substrate material. For example, it is common to insert an underfill material into the space between the IC and the package substrate, to fill the gaps around the solder balls. The underfill may have a CTE that is intermediate between the CTE of the IC and the CTE of the package substrate.
The continued decrease in IC dimensions has led to the use of low dielectric constant (low-k) materials (e.g., SiOC, SiOCN or SiCOH) to form the inter-metal dielectric (IMD) interconnect layers. For smaller technology nodes, foundries have considered the use of extreme low k (ELK) dielectric materials having a dielectric constant k of 2.6 or less. A common method for providing an ELK dielectric is to form a porous layer of dielectric, because the air in the pores has a dielectric constant of 1.0, reducing the overall average value of k for the ELK layer. Unfortunately, the introduction of pores renders the ELK dielectric layer more brittle, and more susceptible to damage from warpage due to CTE mismatch.
Improved methods of protecting the IMD layers is desired.